1. Field of the Invention
The present invention relates to a semiconductor device having a configuration in which a semiconductor element and a chip component are mounted on inner leads, and the resultant structure is sealed with a molding resin.
2. Description of the Related Art
A semiconductor device having a quad flat package (referred to as QFP) structure or the like includes a semiconductor chip on which an integrated circuit is formed and a conductor called as a lead frame. The semiconductor chip is mounted on an island of the lead frame, and pads provided on the semiconductor chip are connected to leads via bonding wires; and then, the resultant structure is sealed with a molding resin. After that, a semiconductor package is separated from the lead frame.
[Patent Document 1] Japanese Patent Application Laid-open No. 2002-231875.
The case where a power supply circuit such as a linear regulator (three terminal regulator) is manufactured as a semiconductor device having the QFP structure will be considered. In this case, a linear regulator stabilizes a power supply voltage input to an input terminal, and outputs the same from an output terminal. Such linear regulator is generally provided with a stabilizing capacitor placed between a power supply terminal and a ground, and between the output terminal and the ground in order to stabilize voltage. Furthermore, in in-vehicle application or the like, there is a case where a decoupling capacitor having several nF to several ten nF in capacitance value is provided in parallel with the stabilizing capacitor in order to comply with a standard called as electro-magnetic compatibility (referred to as EMC).
In a regulator of the QFP structure, the decoupling capacitor needs to be provided on a PCB (Printed Circuit Board), outside the QFP. Therefore, there is a problem in that decoupling characteristics deteriorate by a parasitic inductance and a parasitic resistance caused by leads and a wiring pattern on the PCB, and EMC characteristics of the linear regulator vary due to the wiring pattern on the PCB.
Such problem, that is, the problem that the characteristics of the semiconductor device are affected by the wiring pattern on the PCB to which the semiconductor device is mounted is likely to be generated irrespective of the EMC characteristics.